1. Field of the Invention
The present invention relates to a storage device including a non-volatile memory, more particularly relates to a speed-up of data transfer in a storage device including a flash memory.
2. Description of the Art
In recent years, flash memories have been attracting attention as storage media of digital still cameras and mobile computer equipment.
A flash memory is a semiconductor memory using tunneling or hot electron acceleration to make electrons pass through a gate insulation film and injecting these into a floating gate or a trap layer to change a threshold value of a cell transistor and thereby store data. Each memory cell can be configured by just one transistor using a stacked gate structure, NMOS structure, or the like, therefore an inexpensive and large capacity memory can be realized. As a representative example thereof, a NAND type flash memory can be explained.
FIG. 1 is a diagram showing an example of the internal configuration of a NAND type flash memory. In the NAND type flash memory of FIG. 1, a plurality of memory units 1-1 to 1-n connected to bit lines BL1 to BLn are arranged in an array (vertically and horizontally). For example, a gate of a selection transistor 2 is connected to a selection gate line SL1, while a gate of a selection transistor 3 is connected to a selection gate line SL2. Further, gates of memory cells N0 to N15 are connected to word lines WL0 to WL15.
The memory cells N0 to N15 have stacked gate structures and store data according to the amounts of charge stored in the floating gates. Namely, when many electrons are stored in a floating gate, the threshold value of the transistor rises, therefore any penetration of current to a memory unit 1 (-1 to -n) from one of the charged bit lines BL1 to BLn is detected at an access circuit including a sense amplifier etc. and data is judged.
Such a NAND type flash memory does not have to provide a contact region to the bit line for each memory cell, therefore is suitable for a particularly large capacity and inexpensive storage device.
In general, the programming speed of a flash memory is very slow. Several hundreds of microseconds are required per cell. Further, data can not be overwritten, therefore it is necessary to erase the data preceding the programming. A time of as long as several milliseconds is taken for this. Such a problem is coped with by parallel processing of many memory cells.
Namely, by simultaneously writing data in a block into for example a memory cell group 5 connected to the same word line WL0 and forming a page unit and by further erasing in a block all of a cell block 6 formed by a page group sharing memory units, the transfer speed of a program is improved.
Specifically, for example ISSCC2002 Draft, p. 106, Session 6.4, discloses a 1 Gb NAND type flash memory having a page size of 2 kbytes and an erasure block size of 128 kbytes (kB). Namely, by erasing a 128 kbyte memory cell group in one memory array in parallel and programming memory cells for each 2 kbytes in parallel, a program transfer speed of 10 MB/s is realized.
Further, in recent years, flash memories have increasingly been made multi-leveled and miniaturized. In order to cope with the drop in the signal amount accompanying this, writing techniques having less adverse influence upon non-selected cells have been studied and put into use.
For example, in NAND type flash memories, ones limiting the writing sequence of pages in the erasure blocks are becoming the mainstream. Japanese Patent Publication (A) No. 2002-260390 etc. disclose a writing routine using the technique called “local self-boost” as one of these. An example of such writing in the NAND type flash memory of FIG. 1 will be explained below.
For example, when writing in a memory cell N1 and injecting electrons into its floating gate, first the word lines WL0 and WL2 before and after the memory cell N1 and sandwiching it therebetween are made 0V, the selection transistor 2 is turned on, and the selection transistor 3 is turned off. Here, the bit line BL1 is made 0V, an adjacent bit line BL2 not for writing is made 3V, the selection word line WL1 is made 20V, and all word lines WL3 to WL15 other than that are boosted up to 10V. When using such a writing routine, the nodes sandwiched between word lines WL0 and WL2 at 0V and linked with the non-selected bit line are disconnected from the other nodes and rise in potential up to about 10V upon receiving coupling from the word line WL1. On the other hand, for the selected memory cell N1, only when the adjacent cell transistor N0 is in a depletion state, the 0V applied to the bit line BL1 is transmitted to a channel of the cell transistor N1 whereby the writing is executed. Namely, when using the writing technique described above, the adjacent cell on the bit line side of a cell for writing is erased and become a depletion state. For this reason, it is essential that the entire block be erased, then write operations be performed sequentially for the memory cells N15, N14, N13, . . . , N0.
In this way, the trend in large capacity flash memories in recent years is not to allow random writing even in page writing and to make sequential writing from a higher address toward a lower address in a block essential.